NoBug recrute un Asic Verification engineer

Expirée

Job Description

We are seeking a verification engineer to work on different projects, and help drive pre-silicon functional verification different designs.

Role:

  • Develop C++ reference models of hardware blocks for functional verification of RTL
  • Develop testbenches, reusable verification components (e.g. BFMs, scoreboards) for functional verification
  • Create functional verification plans
  • develop and debug constrained-random and directed testcases towards coverage driven verification closure
  • Develop/maintain simulation flow

Required Skills / Experience:

  • 2+ years in RTL design and verification, with an emphasis on verification
  • worked in  block-level and/or system-level verification
  • worked C++ and/or SystemC modeling
  • Strong Unix and scripting knowledge – Perl, Python, TCL, bash, c-shell
  • Strong knowledge of SystemVerilog
  • Familiarity with uVM, eRM, VMM methodologies (from higher to lower interest)
  • Knowledge of Hardware/software co-simulation
  • Preparing detailed verification plans
  • Developing, testing, and integrating C++/SystemC models
  • Developing verification components
  • Executing metric-driven functional verification using random stimulus coupled with covergroups and SystemVerilog Assertions.
  • The successful candidate needs to be highly pro-active, and be willing to help address whatever design and verification issues arise.

 

Required  skills:

-uVM, eRM, VMM methodologies

-Knowledge of Digital Integrated Circuits Knowledge of Hardware Description Languages (VHDL/Verilog)

Desired Skills:

  • Prior verification experience with serial interfaces such as USB, PCIE, I2C, I2S, SPI etc.

Educational Requirements:

  • Graduate Computer Science/Electronics/Mathematics Proficiency with OOP
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